Conventionally, a Group III nitride semiconductor formed on a substrate has been used as a functional material for fabricating pn-junction Group III nitride semiconductor light-emitting devices which emit visible light of short wavelength such as light-emitting diodes (LEDs) and laser diodes (LDs) (see, for example, Japanese Patent Application Laid-Open (kokai) No. 2000-332364). For example, in fabrication of an LED emitting near-UV light, blue light, or green light, n-type or p-type aluminum gallium nitride (AlXGaYN, 0≦X, Y≦1, X+Y=1) is employed for forming a cladding layer (see, for example, Japanese Patent Application Laid-Open (kokai) No. 2003-229645). Similarly, gallium indium nitride (GaYInZN, 0≦Y, Z≦1, Y+Z=1) is employed for fabricating a light-emitting layer (see, for example, Japanese Patent Publication (kokoku) No. 55-3834).
Generally, in conventional Group III nitride semiconductor light-emitting devices, an n-type or a p-type Group III nitride semiconductor layer serving as a cladding layer is joined to a light-emitting layer, in order to fabricate a light-emitting member having a hetero-junction structure for attaining high emission intensity. For example, in order to fabricate a light-emitting member having a doublehetero-junction structure, the light-emitting layer is composed of a semiconductor such as GaYInZN (0≦Y, Z≦1, Y+Z=1), to which an n-type or a p-type Group III nitride semiconductor layer serving as a cladding layer is joined (see, for example, a book written and edited by Isamu AKASAKI, “Group III-V Compound Semiconductors,” published Baifukan Co., Ltd., Chapter 13, May 20 (1995)).
Conventionally, an n-type Group III nitride semiconductor layer interposed between, for example, a substrate and a light-emitting layer, is usually formed from a silicon (Si)-doped Group III nitride semiconductor. In this connection, a semiconductor layer; for example, an Si-doped n-type AlXGaYN (0≦X, Y≦1, X+Y=1) layer having a resistivity controlled through modification of the amount of silicon (Si) as a dopant, is employed (see, for example, Japanese Patent No. 3383242).
From the standpoint of maintaining stable crystallinity and electric properties up to a relatively high concentration, Si is frequently used as an n-type impurity accompanied, however, by a problem of causing cracks when having been doped in large amounts. As n-type impurities other than silicon, on the other hand, there have been known germanium (Ge), sulfur (S), tin (Sn), selenium (Se) and tellurium (Te) (see, for example, Japanese Patent Application Laid-Open (kokai) No. 4-170397 and Japanese Patent No. 3504976). When compared with the case of Si, however, the doping efficiency is low, which is not advantageous for obtaining an n-type Group III nitride semiconductor layer of a low resistance. For example, when doped with Ge at a high concentration to obtain an n-type Group III nitride semiconductor layer of a low resistance, there occurs a defect of generating small holes (pits), in the surface of the n-type Group III nitride semiconductor layer, to impair the flatness.
When a device is produced by forming a light-emitting layer or other pn junction on a layer that is doped with n-type impurities, the generation of pits, even when they are tiny, triggers a problem of leakage of current and deteriorates an electrostatic breakdown voltage.
To improve the electrostatic breakdown voltage, there has been known an art of which the essential point is that “the n-side nitride semiconductor layer includes n-side multiplicity of layers formed by the lamination of at least two kinds of nitride semiconductor layers having the same composition and being doped with the n-type impurities at different concentrations” (see Japanese Patent No. 3063756). In this patent document, the effect of the plurality of layers forming the n-side multiplicity of layers doped at different concentrations is that “crystal defects occurring from the substrate can be terminated, and the crystallinity can be improved in the layer grown on the multiplicity of layers”. That is, what is intended to be decreased by this technology is the dislocation occurring from the substrate but not the dislocation or pits occurring in the layer of a high impurity concentration in the n-type semiconductor layer itself. In this technology, the n-side multiplicity of layers start with an undoped layer and terminate with a layer of a high impurity concentration where the dislocation and pits tend to occur.